1. Field of the Invention
The present invention relates to an image processing device and an image processing method, and, in particular, an image processing device and an image processing method of processing images to be displayed on a display device.
Recently, a CRT (Cathode Ray Tube) display device has been widely used as a display device of a host computer such as a personal computer, a work station or the like. However, a flat-panel display devices such as a liquid crystal panel, a plasma display device and so forth have drawn attentions.
A signal provided from a personal computer to a CRT display device or a flat-panel display device is a video signal. The video signal generally includes analog image data, vertical and horizontal synchronization signals (VS, HS signals), or a composite signal which is a combination of these signals.
Such a video signal may have any of different specifications. Sometimes, a personal computer renders a plurality of different resolutions. As these specifications, there are various resolutions such as 320 dotsxc3x97200 dots, 640xc3x97400 dots, 720 dotsxc3x97400 dots, 640 dotsxc3x97350 dots, 640 dotsxc3x97480 dots, 800 dotsxc3x97600 dots, 1024 dotsxc3x97768 dots, 1280 dotsxc3x971024 dots, and so forth.
A so-called multi-sync CRT display device is used for dealing with these resolutions. The multi-sync CRT display device measures the synchronization signals of the video signal, causes a driving period and a moving width of a scanning line to correspond to the synchronization signals of the video signal, and, thereby, deals with the resolutions. This is possible because the pitch of a shadow mask which determines the minimum display pixel of the CRT display device is smaller than the pixel pitch according to the display resolution of the video signal.
However, with regard to dot-matrix display devices such as a liquid crystal penal, a plasma display device and so forth, because the pixel thereof is larger than that of the shadow mask of the CRT, the processing performed by the multi-sync CRT display device cannot be performed by the dot-matrix display device. Therefore, analog-to-digital conversion is performed on the input analog video signal in synchronization with the resolution (dot clock signal) of the input analog video signal, interpolation is performed so as to generate a signal corresponding to the output resolution of the dot-matrix display device in each of horizontal and vertical directions, and, thereby, display is made by the display device.
2. Description of the Related Art
FIG. 1 is a block diagram showing one example of an image display device in the related art.
In FIG. 1, the image display device 20 is a device of driving a dot-matrix display device using an analog image signal, and, performs display based on the image signal from a personal computer 10. The personal computer 10 includes a VGA (Video Graphics Array) controller 11 built therein. The image signal is provided to the image display device 20 via the VGA controller 11.
The VGA controller 11 provides RGB (Red, Green, Blue) signals 12, HS (Horizontal Scan) and VS (Vertical Scan) signals 13 according to the images, to the image display device 20.
The image display device 20 includes an A-D converter 21, an image processing part 22, an LCD panel 23, PLL (Phase Locked Loop) circuits 24, 26, and a system control part 25.
The analog video signals (RGB signals 12 and HS and VS signals 13) are provided to the A-D converter 21, and the HS and VS signals 13 are also provided to the system control part 25.
The A-D converter 21 converts the analog video signals from the VGA controller 11 into digital signals in synchronization with a clock signal from the PLL circuit 24.
The system control part 25 controls the PLL circuits 24, 26, A-D converter 21 and image processing part 22 in synchronization with the HS and VS signals 13.
The PLL circuit 24 provides a clock signal in phase with the HS and VS signals from the system control part 25, to the A-D converter 21, and controls the conversion timing of the A-D converter 21.
The PLL circuit 26 provides the clock signal in phase with the HS and VS signals from the system control part 25, to the image processing part 22 and LCD panel 23, and controls the driving timing of the image processing part 22 and LCD panel 23.
The image processing part 22 converts the digital signals given from the A-D converter 21 into signals of resolution corresponding to the LCD panel 23 using a control signal from the system control part 25 and the clock signal from the PLL circuit 26. The image processing part 22 includes a FIFO (First-In-First-Out) built therein, and stores the thus-converted signals into the FIFO. These image signals are provided to the LCD panel 23.
The LCD panel 23 holds data of the image signals given by the image processing part 22 in response to the clock signal given by the PLL circuit 26, and performs display based on the held data.
FIG. 2 is a block diagram showing another example of an image display device in the related art.
In FIG. 2, the image display device 30 is a device of driving a dot-matrix display device using digital image signals, and, performs display based on the image signals from a personal computer 15. The personal computer 15 includes a VGA (Video Graphics Array) controller 16 built therein. The image signals are provided to the image display device 30 via the VGA controller 16. The VGA controller 16 provides the RGB (Red, Green, Blue) signal 17, DE (Data Enable), CLK, HS and VS signals 18 according to the images, to the image display device 30.
The image display device 30 includes an image processing part 31, an LCD panel 32, a PLL (Phase Locked Loop) circuit 34 and a system control part 33.
The video signals (RGB signal 17 and DE, CLK, HS and VS signals 18) are provided to the image processing part 31, and DE, CLK, HS and VS signals 18 are also provided to the system control part 33.
The system control part 33 controls the PLL circuit 34 and image processing part 31 in synchronization with the DE, CLK, HS and VS signals 18.
The PLL circuit 34 provides a clock signal in phase with the DE, CLK, HS and VS signals from the system control part 33, to the image processing part 31 and LCD panel 32, and controls the driving timing of the image processing part 31 and LCD panel 32.
The image processing part 31 converts the digital signals given from the VGA controller 16 into signals of resolution corresponding to the LCD panel 32 using a control signal from the system control part 33 and the clock signal from the PLL circuit 34. The image processing part 31 includes a FIFO (First-In-First-Out) built therein, and stores the thus-converted signals into the FIFO. These image signals are provided to the LCD panel 32.
The LCD panel 32 holds data of the image signals given by the image processing part 31 in response to the clock signal given by the PLL circuit 32, and performs display based on the held data.
FIGS. 3A through 3F show waveforms of the digital signals in the related art.
FIG. 3A shows the VS signal input to the image processing part 31 shown in FIG. 2; FIG. 3B shows the DE signal; FIGS. 3C and 3D show the HS signal, FIG. 3E shows the video (RGB) signal and FIG. 3F shows the DE signal. In this example, it is assumed that the input video signal is of VGA mode (640xc3x97480 dots, 75 Hz), for example.
The VS signal shown in FIG. 3A has a pulse wave having a period of 13.3 ms. When the VS signal has the high level, a vertical scanning signal updating an image is input.
The DE signal shown in FIG. 3B has a synchronization interval when the VS signal has the low level, and has a vertical back-porch interval immediately after the VS signal rises up from the low level to the high level. The DE signal has a vertical effective image interval after the vertical back-porch interval has elapsed. The vertical effective image interval of the DE signal is 12.8 ms (for 480 lines). The DE signal has a vertical front-porch interval after the vertical effective image interval has elapsed, until the VS signal decays down from the high level to the low level.
The HS signal shown in FIGS. 3C and 3D has a pulse wave having a period of 26.7 xcexcs. When the HS signal has the high level, a horizontal scanning signal for scanning in the horizontal direction of the image is input.
The video (RGB) signal shown in FIG. 3E has effective data after a horizontal synchronization interval (for 64 pixels) of the low level of the pulse of the HS signal and a horizontal back-porch interval (for 120 pixels) starting from the rising up of the HS signal have elapsed. The video signal comes to have effective data during a horizontal effective image interval (for 640 pixels), and is effective during this interval. After the horizontal effective image interval of the video signal, a horizontal blanking interval (horizontal retrace/fly-back interval) starts preceding the time the HS signal decays from the high level to the low level by a horizontal front-porch interval (for 16 pixels). The DE signal shown in FIG. 3F has the high level while the video signal is effective.
As mentioned above, the clock signal used for driving the LCD panel 23/32 is generated by the PLL circuit 26/34 in each of the image display devices shown in FIGS. 1 and 2.
Thus, in the image display devices in the related art, the predetermined frequency for determining the timing of reading of the image data to be output to the LCD panel is determined according to the respective resolutions of the video signals given from the personal computer. This determination is performed by the system control part 25/33 including a CPU, a memory, and programs stored in the memory, not shown in the figures. For this process, programming has been previously made such that examination is performed previously only for the video signals which are previously expected to be input, and the interpolation (conversion) processing according to the output resolutions are performed. Accordingly, it is not possible to deal with the video signals other than those which are perilously expected to be input.
Thus, control in accordance with input variation in the video signal is not performed. Therefore, the timing of reading of the image data from the FIFO in the actual interpolation (conversion) processing according to the output resolution is severe. As a result, it is necessary that a plurality of types of the reading timings are set within the allowable range of the LCD panel. Thereby, the PLL should be able to output the plurality of frequencies variably, for the timings of reading the image data from the FIFO.
However, the PLL has a complicated function such that the frequency of the output clock signal is changed in accordance with input conditions. Therefore, jitter may easily occur such that the phase of the output clock signal changes. Due to the jitter, the timing of taking in of the image data by the LCD panel becomes severe, and, thereby, error may occur in the image data, and flickering may occur in the displayed image.
In order to solve this problem, it can be considered to provide the FIFO having a sufficient capacity such as that for one frame, for example. However, because the FIFO is expensive, this method is not practical.
An object of the present invention is to solve this problem, and to provide an image processing device and an image processing method by which precise image processing can be performed with a memory having a small capacity, and the device can be simplified.
An image processing device according to the present invention comprises:
a storing part storing image data of an input image signal; and
a control part detecting a resolution of the image data from a synchronization signal which is in synchronization with the input image signal, and, controlling timing of reading the image data from the storing part according to the thus-detected resolution.
Thereby, the resolution of the image data is detected according to variation in the input image signal, and the timing of reading the image data from the storing part is controlled accordingly. As a result, it is possible to perform image processing properly without providing a PLL circuit which can output various frequencies through control, and with a FIFO having a small capacity. Thus, it is possible to simplify the image display device.
The control part may have a data enable signal input thereto as the synchronization signal which is in synchronization with the input image signal, detect the number of data enable signal pulses within one frame of the input image signal in the data enable signal, and determine, as a magnification in a vertical direction, a value obtained as a result of a resolution in the vertical direction of an image to be output being divided by the above-mentioned number of data enable signal pulses within one frame;
the data enable signal which is in synchronization with the input image signal and a clock signal which is in synchronization with the reading timing for the image data may be provided to the control part;
a pulse width of the data enable signal may be counted by using the clock signal, and, the value obtained as a result of the resolution in a horizontal direction of the image to be output being divided by a thus-obtained count value may be determined as a magnification in the horizontal direction, by the control part; and
the control part may control the timing of reading the image data from the storing part according to the thus-obtained magnification in the vertical direction and magnification in the horizontal direction.
Thereby, the control part detects the number of data enable signal pulses as the synchronization signal which is in synchronization with the input image signal, and controls the timing of reading of the image data from the storing part according to the magnification in the vertical direction and magnification in the horizontal direction detected by using the thus-detected number of the data enable signal pulses and count value of the pulse width thereof. Thereby, it is possible to perform image processing properly without providing a PLL circuit which can output various frequencies through control, and with a FIFO having a small capacity.
An image processing device according to another aspect of the present invention, comprises:
a storing part storing image data of an input image signal; and
a control part detecting periods of a horizontal synchronization signal and vertical synchronization signal which are in synchronization with the input image signal,
determining a magnification for an image to be output, from a horizontal synchronization interval and a vertical synchronization interval for the image to be output, and the periods of the horizontal synchronization signal and vertical synchronization signal which are in synchronization with the input image signal; and
controlling timing of reading the image data from the storing part according to the thus-determined magnification.
Thereby, the magnification for the image to be output is detected from the horizontal synchronization interval and vertical synchronization interval for the image to be output, and the periods of the horizontal synchronization signal and vertical synchronization signal which are in synchronization with the input image signal, and the timing of reading the image data from the storing part is controlled according to the thus-determined magnification. Thereby, it is possible to perform image processing properly without providing a PLL circuit which can output various frequencies through control, and with a FIFO having a small capacity.
The device may further comprise a clock generating part generating a predetermined clock signal according to the resolution of the image to be output; and
the control part may read the image data from the storing part in synchronization with the clock signal generated by the clock generating part.
Thereby, it is possible to perform image processing properly without providing a PLL circuit which can output various frequencies through control, and with a FIFO having a small capacity.
The control part may count an interval obtained as a result of a vertical blanking interval being removed from one frame of the image signal, using the clock signal generated by the clock generating part,
set, as a horizontal blanking interval for the image to be output, a value obtained from dividing the thus-obtained count value by a resolution in the vertical direction of the image to be output, and subtracting a resolution in the horizontal direction of the image to be output from the division result, and
read the image data from the storing part according to the thus-set horizontal blanking interval and the above-mentioned magnification.
Thereby, it is possible to perform image processing properly without providing a PLL circuit which can output various frequencies through control, and with a FIFO having a small capacity.
The control part may update the horizontal blanking interval for each frame of the input image signal.
Thereby, it is possible to perform reading the image data from the storing part with a FIFO having a small capacity as the storing part.
The control part may update the horizontal blanking interval according to a difference between a writing time and a reading time for the storing part.
Thereby, it is possible to perform reading the image data from the storing part with a FIFO having a small capacity as the storing part.
The control part may update the horizontal blanking interval according to a data amount of the storing part.
Thereby, it is possible to perform reading the image data from the storing part with a FIFO having a small capacity as the storing part.
An image processing method according to the present invention, comprises the steps of:
a) storing image data of an input image signal in a storing part; and
b) detecting a resolution of the image data from a synchronization signal which is in synchronization with the input image signal, and, controlling timing of reading the image data from the storing part according to the thus-detected resolution.
Thereby, the resolution of the image data is detected according to variation in the input image signal, and the timing of reading the image data from the storing part is controlled accordingly. As a result, it is possible to perform image processing properly without providing a PLL circuit which can output various frequencies through control, and with a FIFO having a small capacity. Thereby, it is possible to simply the display device.
Other objects and further features of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.